The invention relates generally to a method for forming a shallow trench isolation (STI) of a semiconductor device, and more specifically, to a method for forming an STI for a three-dimensional structured transistor to improve integration and operation reliability of the device.
Due to the high degree of integration of memory devices, a three-dimensionally structured cell is formed to increase the length of channels. Specifically, a recess gate structure where a gate part is formed in an active region is formed to increase channel length.
In the above-described structure, it is important to control the presence of a pointed silicon horn that may remain in the semiconductor substrate of a boundary portion of an active region and a device isolation region.